library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;


entity TB_gle_mips is
end TB_gle_mips;

architecture TEST of TB_gle_mips is
component gle_mips is
generic (		NUMBIT	: integer := 32;
			OPSIZE	: integer := 6;
			REGSIZE	: integer := 5;
			ROMSIZE	: integer := 48;
			RAMSIZE	: integer := 6);
port(	clock	 			: in   std_logic;
		reset	 			: in   std_logic;
		TEST_CU_en_if 	 	: out std_logic;
		TEST_CU_en_id 	 	: out std_logic;
		TEST_CU_en_ex 	 	: out std_logic;
		TEST_CU_en_mm 	 	: out std_logic;
		TEST_IF_opcode		: out std_logic_vector (OPSIZE-1 downto 0);
		TEST_IF_r_s 			: out std_logic_vector (REGSIZE-1 downto 0);
		TEST_IF_r_t 			: out std_logic_vector (REGSIZE-1 downto 0);
		TEST_IF_r_d 			: out std_logic_vector (REGSIZE-1 downto 0);
		TEST_IF_Imm 			: out std_logic_vector (NUMBIT/2-1 downto 0);
		TEST_IF_shamt  		: out std_logic_vector (REGSIZE-1 downto 0);
		TEST_IF_func  		: out std_logic_vector (OPSIZE-1 downto 0);
		TEST_IF_NPC_out		: out std_logic_vector (NUMBIT-1 downto 0);
		final_result			: out std_logic_vector (NUMBIT-1 downto 0)
);
end component;

type STATE_T is (IFs,ID,EX,MM,WB);

signal CLK : std_logic := '0';
signal RST : std_logic;

signal a,b,c,d : std_logic;
signal state : STATE_T;
signal I_opcode	: std_logic_vector (5 downto 0);
signal I_r_s 		: std_logic_vector (4 downto 0);
signal I_r_t 		: std_logic_vector (4 downto 0);
signal I_r_d 		: std_logic_vector (4 downto 0);
signal I_Imm 		: std_logic_vector (15 downto 0);
signal I_shamt  	: std_logic_vector (4 downto 0);
signal I_func  		: std_logic_vector (5 downto 0);
signal I_NPC_out	: std_logic_vector (31 downto 0);


signal result : std_logic_vector(31 downto 0);
begin

CPU_UUT: gle_mips generic
	map (	NUMBIT	=> 32,
			OPSIZE	=> 6,
			REGSIZE	=> 5,
			ROMSIZE	=> 48,
			RAMSIZE	=> 6 ) port
	map(	clock	 		=> CLK,
			reset	 		=> RST,
			TEST_CU_en_if 	=> a,
			TEST_CU_en_id 	=> b,
			TEST_CU_en_ex 	=> c,
			TEST_CU_en_mm 	=> d,
			TEST_IF_opcode	=> I_opcode,
			TEST_IF_r_s 		=> I_r_s,
			TEST_IF_r_t 		=> I_r_t,
			TEST_IF_r_d 		=> I_r_d,
			TEST_IF_Imm		=> I_Imm,
			TEST_IF_shamt	=> I_shamt,
			TEST_IF_func		=> I_func,
			TEST_IF_NPC_out	=> I_NPC_out,
			final_result		=> result
		);

CLK_P: process (CLK)
	begin
		CLK <= not (CLK) after 150 ns;
	end process;

RST		<=	'1', '0' after 120 ns;

state	<=	IFs when a = '1' else
			ID when b = '1' else
			EX when c = '1' else
			MM when d = '1' else
			WB;

end TEST;
